1. Field of the Invention
Embodiments of the invention relate to vertical semiconductor devices having high breakdown voltages.
2. Description of the Related Art
In general, semiconductor devices are of a lateral type, having an electrode portion on one surface, or a vertical type, having an electrode on both surfaces. A vertical semiconductor device is such that the direction in which a drift current flows when in an on-state and the direction in which a depletion layer caused by reverse bias voltage extends when in an off-state are the same. For example, in the case of a normal planar type n-channel vertical MOSFET, a high resistance n−-type drift layer works as a region that causes a drift current to flow in a vertical direction when the MOSFET is in an on-state, and depletes when the MOSFET is in an off-state, thereby working to increase breakdown voltage. By the thickness of the high resistance n−-type drift layer being reduced, thus shortening the current path, drift resistance decreases. Consequently, there is an advantage in that the actual on-state resistance of the MOSFET is reduced. On the other hand, however, the spread of the depletion layer spreading in the n−-type drift region narrows, because of which breakdown voltage decreases.
Meanwhile, a semiconductor device with high breakdown voltage is such that it is necessary to thicken the n−-type drift layer in order to maintain the breakdown voltage. Therefore, on-state resistance rises, and on-state loss increases. In this way, on-state resistance and breakdown voltage are in a trade-off relationship.
It is known that this trade-off relationship is established in a vertical semiconductor device such as an IGBT, bipolar transistor, or diode. Also, this trade-off relationship is the same in the case of a lateral semiconductor device. A vertical semiconductor device with a superjunction structure having a drift layer configured of parallel pn layers, wherein an n-type region with an increased impurity concentration and a p-type region are disposed alternately, is known as a method of improving the trade-off relationship.
FIGS. 25A and 25B show a plan view and sectional view of an existing vertical semiconductor device 500 having a superjunction structure. FIG. 25A shows one portion of a plan view, while FIG. 25B is a sectional view along X-X′ of FIG. 25A. Herein, a case is shown wherein the widths of parallel pn layers 60 disposed under a source pad electrode 56 and under a gate pad electrode 57 are the same.
The vertical semiconductor device 500 includes an active region 53 and a voltage withstanding structure region 52 disposed in a peripheral portion outside the active region 53. A gate pad region 54 (inside the two-dot chain line shown in FIG. 25A) is disposed in the active region 53. P-type well regions 55 are disposed in the active region 53, and a source pad electrode 56 is disposed on the upper surfaces of the p-type well regions 55 of the active region 53 other than in the gate pad region 54. The p-type well regions 55 are formed so as to enclose the active region 53 in an outer peripheral end inside the active region 53, and a gate runner 58 connected to the gate pad electrode 57 is disposed on the upper surfaces of the p-type well regions 55.
The planar form of a gate electrode 59 disposed under the source pad electrode 56 is a stripe form extending in a direction Q of FIG. 25A, and is disposed extending to the whole of a region under the gate pad electrode 57. The direction Q of FIG. 25A indicates a direction vertical to the direction in which a p-type partition region 60a and n-type drift region 60b of the parallel pn layers 60, to be described hereafter, are repeatedly alternately disposed.
The p-type well region 55 is disposed in a surface layer of a first n−-type drift region 69 under the source pad electrode 56 and under the gate pad electrode 57. An n+-type source region 61 and p+-type contact region 62 are disposed in a surface layer of the p-type well region 55. The p-type partition region 60a is disposed in contact with the p-type well region 55 under the p-type well region 55. The gate electrode 59 is disposed across a gate insulating film 68 on the p-type well region 55 sandwiched between the n+-type source region 61 and first n−-type drift region 69. The gate electrode 59 is also disposed extending under the gate pad electrode 57. The n+-type source region 61 and p+-type contact region 62 under the source pad electrode 56 are connected to the source pad electrode 56 disposed above. Also, the gate electrode 59 under the source pad electrode 56 is electrically isolated from the source pad electrode 56 by an interlayer dielectric 64, and an outer peripheral portion thereof is connected via a contact hole 65 to the gate runner 58.
As previously described, MOS structures J of the same dimensions are formed inside the active region 53 and inside the gate pad region 54, and the p-type partition region 60a connected to the p-type well region 55 is formed under the p-type well region 55. The width of the p-type partition region 60a is the same below the source pad electrode 56 and below the gate pad electrode 57. Dotted lines parallel to the direction Q shown in FIG. 25A are lines schematically showing the gate electrode 59. The MOS structure of the J portion is configured of the p-type well region 55, n+-type source region 61, gate insulating film 68, and gate electrode 59.
The n+-type source region 61 and p+-type contact region 62 under the gate pad electrode 57 extend in the direction Q of FIG. 25A, and are connected to the source pad electrode 56.
The vertical semiconductor device 500 is such that the drift layer is not configured uniformly of a single conductivity type, but rather is configured of the plurality of parallel pn layers 60 wherein the vertical layer form n-type drift region 60b (n-type column) and vertical layer form p-type partition region 60a (p-type column) are alternately repeatedly joined.
By increasing the impurity concentration of the n-type drift region 60b configuring the parallel pn layers 60, thus reducing the on-state resistance and achieving charge balance of the n-type drift region 60b and p-type partition region 60a, it is possible to cause the whole of the parallel pn layers 60 to deplete, thus increasing breakdown voltage. Because of this, it is possible to improve the trade-off relationship. Achieving charge balance means determining each impurity concentration so that the width of the depletion layer spreading inside the n-type drift region 60b and the width of the depletion layer spreading inside the p-type partition region 60a are the same, whereby the whole of the parallel pn layers 60 depletes at a rated voltage or less.
In Japanese Patent Application Publication No. JP-A-2009-99911 (also referred to herein as “JP-A-2009-99911”), it is described that, in order to suppress the generation of avalanche carriers under the gate pad electrode, thus achieving a reduction in on-state resistance, a MOS structure portion is formed immediately below the gate pad electrode, and the impurity concentration of the n-type column and p-type column is lower than that under the source electrode.
Also, in Japanese Patent Application Publication No. JP-A-2001-298191 (also referred to herein as “JP-A-2001-298191”), it is described that, in order to suppress avalanche breakdown in a portion immediately below the gate pad electrode, thus maintaining stable breakdown voltage, a p-type well region is included immediately below the gate pad electrode, the pitch of parallel pn layers connected to the p-type well region under the p-type well region is shorter than in the active region, and the impurity concentration is lower than in the active region.
A vertical semiconductor device having this superjunction structure is such that an end portion of the p-n junction of the parallel pn layers is connected to the p-type well region, because of which a good charge balance is obtained, and dynamic avalanche breakdown, which is liable to occur when turning off, is unlikely to occur.
Also, in Japanese Patent Application Publication No. JP-A-2005-150348 (also referred to herein as “JP-A-2005-150348”), it is described that in a planar type semiconductor device, a MOSFET cell structure is also formed under the gate pad electrode.
FIGS. 26 and 27 show the flow of carriers (electrons 74) when turning off the vertical semiconductor device 500 shown in FIGS. 25A and 25B.
FIG. 26 is a diagram showing the flow of the electrons 74 in an on-state before entering a turn-off operation. In the on-state, electrons 74 flowing out from the source pad electrode 56 to the n+-type source region 61 are implanted through a channel inversion layer 67 into the first n−-type drift region 69, and flow via the n-type drift region 60b into an n+-type drain region 71. At this time, electrons 74 flowing out from the n+-type source region 61 in a peripheral portion of the active region 53 are prevented in the p-type partition region 60a immediately below the gate pad electrode 57 from spreading in the direction in which the p-type partition region 60a and n-type drift region 60b of the parallel pn layers 60 are alternately repeated (the lateral direction of a dotted arrow in the drawing). Because of this, a vertical semiconductor device wherein the parallel pn layers 60 are not formed in the drift layer is such that on-state resistance is higher than when the flow of the electrons 74 spreads in the same direction (dotted arrows in the drawing) as the direction in which the parallel pn layers 60 are repeated (shown by a lateral dotted arrow in the drawing), and the trade-off relationship between the on-state resistance and breakdown voltage is not necessarily a preferred relationship.
FIG. 27 is a diagram showing a state wherein a shift is made to a turn-off operation, and the voltage rises. A depletion layer 81 indicated by dotted lines begins to spread from a p-n junction 80, indicated by a heavy line (herein, the heavy line shows only one place), configured of the p-type well region 55 and p-type partition region 60a and the first n−-type drift region 69, second n−-type drift region 72, and n-type drift region 60b. Electrons 74 left by the depletion layer 81 are swept out to the n+-type drain region 71.
When the current density during the turn-off operation is high at, for example, 100 A/cm2, and the electrical field intensity inside the depletion layer 81 in this state increases, dynamic avalanche occurs. Holes 83 generated in large quantity by the dynamic avalanche flow through the p-type well region 55 and p+-type contact region 62 into the source pad electrode 56. However, holes 83 infiltrating the p-type well region 55 and p+-type contact region 62 under the gate pad electrode 57 move a long distance to the source pad electrode 56, which is in the direction Q. Because of this, the potentials of the p-type well region 55 and p+-type contact region 62 under the center of the gate pad electrode 57 rise due to direction Q resistance R of the p-type well region 55 and p+-type contact region 62, and there is false firing of a parasitic npn transistor configured of the n+-type source region 61, p-type well region 55, and n-type drift region 60b of a portion E. A large amount of follow current flows due to the false firing, causing destruction. That is, turn-off (dynamic avalanche) withstand decreases. Meanwhile, as holes 83 flowing into the p-type well region 55 and p+-type contact region 62 under the source pad electrode 56 are pulled out by the source pad electrode 56 immediately above the p+-type contact region 62, this phenomenon does not occur.
Also, holes 83 generated inside the depletion layer 81 exhibit the same behavior in the case of a static avalanche too, causing avalanche withstand under the gate pad electrode 57 to decrease.
FIGS. 28 and 29 are diagrams showing a reverse recovery phenomenon of the parasitic diode of the vertical semiconductor device 500 of FIGS. 25A and 25B. FIG. 28 shows a state wherein forward current is flowing through the parasitic diode. FIG. 29 shows a state wherein reverse recovery of the parasitic diode is occurring.
In FIG. 28, holes 83 implanted from the source pad electrode 56 into the p-type well region 55 flow into the second n−-type drift region 72 through the p-n junction 80 configured of the p-type well region 55 and p-type partition region 60a and the first n−-type drift region 69, second n−-type drift region 72, and n-type drift region 60b. Meanwhile, electrons 74 implanted from the n+-type drain region 71 into the second n−-type drift region 72 flow into the p-type partition region 60a through the n-type drift region 60b. Due to the holes 83 and electrons 74, conductivity modulation occurs in the parallel pn layers 60 (inside a circle 90), and excess carriers accumulate.
In FIG. 29, the depletion layer 81 spreads from the p-n junction 80 when reverse recovery occurs, and excess holes 83 are swept out to the source pad electrode 56 via the p-type well region 55 and p+-type contact region 62. Meanwhile, excess electrons 74 are swept out to the drain electrode 73 via the n+-type drain region 71. When the electrical field intensity inside the depletion layer 81 increases in a state wherein a large number of carriers exist, dynamic avalanche occurs. A large number of holes 83 generated by the dynamic avalanche under the gate pad electrode 57 flow to the source pad electrode 56, which is in the direction Q. Thereupon, as illustrated in FIG. 27, there is false firing of the parasitic npn transistor of the portion E under the gate pad electrode 57. Because of this, dynamic avalanche withstand decreases.
It is supposed that the phenomena illustrated in FIGS. 26 to 29 also occur in JP-A-2009-99911 and JP-A-2001-298191. Also, in JP-A-2005-150348, the element is a planar type element, not a superjunction type element. Also, by the region immediately below the gate pad electrode being an active region, it is possible to reduce on-state resistance, but when using only this method, the current path is limited to the direction in which the p-type well region extends. Because of this, there is a problem in that the current density increases at the termination of the n+-type source region (the place in which the n+-type source region is connected to the source electrode disposed opposing the gate pad electrode) immediately below the gate pad electrode when turning off, the electrical field intensity inside the depletion layer increases, and dynamic avalanche is liable to occur.
Thus, as is described above, certain shortcomings exist in the related art.